1. Field of the Invention
Generally, the present disclosure relates to the manufacturing of semiconductor devices, and, more specifically, to various methods of forming fins for FinFET semiconductor devices and the selective removal of some of the fins.
2. Description of the Related Art
In modern integrated circuits, such as microprocessors, storage devices and the like, a very large number of circuit elements, especially transistors, are provided and operated on a restricted chip area. Immense progress has been made over recent decades with respect to increased performance and reduced feature sizes of circuit elements, such as transistors. However, the ongoing demand for enhanced functionality of electronic devices forces semiconductor manufacturers to steadily reduce the dimensions of the circuit elements and to increase the operating speed of the circuit elements. The continuing scaling of feature sizes, however, involves great efforts in redesigning process techniques and developing new process strategies and tools so as to comply with new design rules. Generally, in complex circuitry including complex logic portions, MOS technology is presently a preferred manufacturing technique in view of device performance and/or power consumption and/or cost efficiency. In integrated circuits including logic portions fabricated by MOS technology, field effect transistors (FETs) are provided that are typically operated in a switched mode, that is, these devices exhibit a highly conductive state (on-state) and a high impedance state (off-state). The state of the field effect transistor is controlled by a gate electrode, which controls, upon application of an appropriate control voltage, the conductivity of a channel region formed between a drain region and a source region.
To improve the operating speed of FETs, and to increase the density of FETs on an integrated circuit device, device designers have greatly reduced the physical size of FETs over the years. More specifically, the channel length of FETs has been significantly decreased, which has resulted in improving the switching speed of FETs. However, decreasing the channel length of a FET also decreases the distance between the source region and the drain region. In some cases, this decrease in the separation between the source and the drain makes it difficult to efficiently inhibit the electrical potential of the source region and the channel from being adversely affected by the electrical potential of the drain. This is sometimes referred to as a so-called short channel effect, wherein the characteristic of the FET as an active switch is degraded.
In contrast to a FET, which has a planar structure, a so-called FinFET device has a three-dimensional (3D) structure. FIG. 1A is a perspective view of an illustrative prior art FinFET semiconductor device “A” that is formed above a semiconductor substrate B that will be referenced so as to explain, at a very high level, some basic features of a FinFET device. In this example, the FinFET device A includes three illustrative fins C, a gate structure D, sidewall spacers E and a gate cap layer F. Trenches T are formed in the substrate B to define the fins C. The gate structure D is typically comprised of a layer of gate insulating material (not separately shown), e.g., a layer of high-k insulating material (k-value of 10 or greater) or silicon dioxide, and one or more conductive material layers (e.g., metal and/or polysilicon) that serve as the gate electrode for the device A. The fins C have a three-dimensional configuration: a height H, a width W and an axial length L. The axial length L corresponds to the direction of current travel in the device A when it is operational. The portions of the fins C covered by the gate structure D are the channel regions of the FinFET device A. In a conventional process flow, the portions of the fins C that are positioned outside of the spacers E, i.e., in the source/drain regions of the device A, may be increased in size or even merged together (a situation not shown in FIG. 1A) by performing one or more epitaxial growth processes. The process of increasing the size of or merging the fins C in the source/drain regions of the device A is performed to reduce the resistance of source/drain regions and/or make it easier to establish electrical contact to the source/drain regions. Even if an epi “merger” process is not performed, an epi growth process will typically be performed on the fins C to increase their physical size.
In the FinFET device, the gate structure D may enclose both the sides and the upper surface of all or a portion of the fins C to form a tri-gate structure so as to use a channel having a three-dimensional structure instead of a planar structure. In some cases, an insulating cap layer (not shown), e.g., silicon nitride, is positioned at the top of the fins C and the FinFET device only has a dual-gate structure (sidewalls only). Unlike a planar FET, in a FinFET device, a channel is formed perpendicular to a surface of the semiconducting substrate so as to reduce the physical size of the semiconductor device. Also, in a FinFET, the junction capacitance at the drain region of the device is greatly reduced, which tends to significantly reduce short channel effects. When an appropriate voltage is applied to the gate electrode of a FinFET device, the surfaces (and the inner portion near the surface) of the fins C, i.e., the vertically oriented sidewalls and the top upper surface of the fin, form a surface inversion layer or a volume inversion layer that contributes to current conduction. In a FinFET device, the “channel-width” is estimated to be about two times (2×) the vertical fin-height plus the width of the top surface of the fin, i.e., the fin width. Multiple fins can be formed in the same foot-print as that of a planar transistor device. Accordingly, for a given plot space (or foot-print), FinFETs tend to be able to generate significantly higher drive current density than planar transistor devices. Additionally, the leakage current of FinFET devices after the device is turned “OFF” is significantly reduced as compared to the leakage current of planar FETs, due to the superior gate electrostatic control of the “fin” channel on FinFET devices. In short, the 3D structure of a FinFET device is a superior MOSFET structure as compared to that of a planar FET, especially in the 20 nm CMOS technology node and beyond. The gate structures D for such FinFET devices may be manufactured using so-called “gate-first” or “replacement gate” (gate-last) manufacturing techniques.
Both FET and FinFET semiconductor devices have an isolation structure, e.g., a shallow trench isolation structure, that is formed in the semiconducting substrate around the device so as to electrically isolate the semiconductor device. Traditionally, isolation structures were always the first structure that was formed when manufacturing semiconductor devices. The isolation structures were formed by etching the trenches for the isolation structures and thereafter filling the trenches with the desired insulating material, e.g., silicon dioxide. After the isolation structures were formed, various process operations were performed to manufacture the semiconductor device. In the case of a FinFET device, this involved masking the previously formed isolation structure and etching the trenches in the substrate that defined the fins. As FinFET devices have been scaled to meet ever increasing performance and size requirements, the width W of the fins C has become very small, e.g., 6-12 nm, and the fin pitch has also been significantly decreased, e.g., the fin pitch may be on the order of about 30-60 nm.
However, as the dimensions of the fins became smaller, problems arose with manufacturing the isolation structures before the fins were formed. As one example, trying to accurately define very small fins in regions that were separated by relatively large isolation regions was difficult due to the non-uniform spacing between various structures on the substrate. One manufacturing technique that is employed in manufacturing FinFET devices is to initially form the trenches T in the substrate B to define multiple “fins” that extend across the substrate, and thereafter remove some of the fins C where larger isolation structures will be formed. Using this type of manufacturing approach, better accuracy and repeatability may be achieved in forming the fins C to very small dimensions due to the more uniform environment in which the etching process that forms the trenches T is performed.
After the trenches T have been formed, some of the fins C must be removed to create room for or define the spaces where isolation regions will ultimately be formed. There are two commonly employed techniques for accomplishing the goal of removing the desired number of fins C. One such removal process is typically referred to as “Fins-cut-First,” as will be described with reference to FIGS. 1B-1E. Accordingly, FIG. 1B depicts the device 10 after a patterned hard mask layer 14, e.g., a patterned layer of silicon nitride, was formed above the substrate 12 in accordance with the desired fin pattern and pitch. In the depicted example, only a single fin will be removed, i.e., the fin 15 corresponding to the feature 14A, to make room for the isolation region. However, as will be recognized by those skilled in the art, depending upon the desired final size of the isolation region, more than one fin may be removed.
FIG. 1C depicts the device 10 after a patterned masking layer 16, e.g., a patterned layer of photoresist, has been formed above the patterned hard mask layer 14. The patterned masking layer 16 has an opening that exposes the feature 14A for removal.
FIG. 1D depicts the device 10 after an etching process has been performed through the patterned masking layer 16 so as to remove the exposed feature 14A of the patterned hard mask layer 14.
FIG. 1E depicts the device 10 after the patterned masking layer 16 was removed and after an etching process was performed through the patterned hard mask layer 14 (without the feature 14A) so as to define full-depth trenches 17 in the substrate 12 that define the fins 15. Due to the removal of the feature 14A, this etching process removes the portions of the substrate 12 that would have otherwise formed a fin 15 in the area under the feature 14A. One problem with the “fin-cut-first” approach is that it inevitably causes different fin sizes, i.e., the dimensions 15X and 15Y are different. This is especially true between fins 15 inside an array of fins and the fins at the edge of the active region that is close to the isolation region. This occurs due to etch loading effects wherein there are different etch rates and etch profiles due to differing patterning densities, pitch, etc.
FIG. 1F depicts the device 10 after several process operations were performed. First, a layer of insulating material 18, such as silicon dioxide, was formed so as to overfill the trenches 17. A chemical mechanical polishing (CMP) process was then performed to planarize the upper surface of the insulating material 18 with the top of the patterned hard mask 14. Thereafter, an etch-back process was performed to recess the layer of insulating material 18 between the fins 15 and thereby expose the upper portions of the fins 15, which corresponds to the final fin height of the fins 15. At this point in the process, the patterned hard mask 14 may or may not be thereafter removed. Next, the gate structure of the device 10 may be formed using either gate-first or gate-last manufacturing techniques.
Another fin removal process is typically referred to as “Fins-cut-Last,” as will be described with reference to FIGS. 1G-1J. FIG. 1G depicts the device 10 after the patterned hard mask layer 14 was formed above the substrate 12 in accordance with the desired fin pattern and pitch. As before, in the depicted example, only a single fin will be removed, i.e., the fin 15 corresponding to the feature 14A, to make room for the isolation region. However, as will be recognized by those skilled in the art, depending upon the desired final size of the isolation region, more than one fin may be removed.
FIG. 1H depicts the device 10 after an etching process was performed through the patterned hard mask layer 14 so as to define full-depth trenches 17 in the substrate 12 that define the fins 15. Note that, in the Fins-cut-Last approach, the size of the fins is very uniform, i.e., the dimension 15A is approximately equal to the dimension 15B. This is primarily due to the fact that, in this approach, fins 15 are formed everywhere on the wafer and there is no undesirable etch loading effects.
FIG. 1I depicts the device 10 after several process operations were performed. First, a layer of insulating material 19, such as silicon dioxide, was formed so as to overfill the trenches 17. Then a CMP process was performed to planarize the upper surface of the layer of insulating material 19 with the patterned hard mask layer 14. Next, a patterned masking layer 22, e.g., a patterned layer of photoresist, was formed above the layer of insulating material 19. The patterned hard mask layer 22 has an opening that exposes the underlying fin for removal.
FIG. 1J depicts the device 10 after one or more etching processes were performed to remove the exposed portions of the layer of insulating material 19, the exposed portions of the hard mask layer 14, i.e., the feature 14A, and the underlying fin 15 by forming a trench 24 in the substrate 12. Inevitably, there will be some tapering of the sidewalls of the trench 24. Although not depicted in the drawings, after the trench 24 is formed, the patterned masking layer 22 will be removed and additional oxide material (not shown) will be formed through the opening 24A in the trench 24 where the fin 15 was removed. Then a chemical mechanical polishing (CMP) process will be performed to planarize the upper surface of all of the insulating materials with the top of the patterned hard mask 14. Thereafter, the isolation regions between devices will be masked and an etch-back process will be performed to recess the layer of insulating material 19 between the fins 15 for each device and thereby expose the upper portions of the fins 15, which corresponds to the final fin height of the fins 15. One problem with the fins-cut-last approach is that if the size (CD) of the opening 24A of the trench 24 is relatively large, then there is less margin for misalignment error when removing the unwanted fin, i.e., there is less margin for error so as to avoid damage to the adjacent fins when the trench 24 is etched. Additionally, although not depicted, if the size of the opening 24A is kept small, there will typically be some residual portion of the fin 15 remaining at the bottom of the trench 24. Conversely, if the size of the opening 24A is increased in an effort to insure complete removal of the unwanted fin at the bottom of the trench 24, then there is a much greater likelihood of damaging the fins adjacent the trench 24 when it is etched. These issues only get worse as the depth of the trench 24 increases.
The present disclosure is directed to various methods of forming fins for FinFET semiconductor devices and the selective removal of some of the fins that may solve or reduce one or more of the problems identified above.